Intel’s ridiculous bet that could reap billions

It’s still a very difficult proposition. “Packaging is not as easy as saying, ‘I want to run 100,000 chips a month,’” says Jim MacGregor, a longtime chip industry analyst and founder of Tireas Research, referring to the continuous flow of chips at different stages of production. “It really comes down to whether it’s Intel or not [packaging] Manufacturers can make deals. “If we see them expanding those operations further, that is an indication that they have done that.”

Last month, Anwar Ibrahim, Malaysia’s prime minister, revealed in a Facebook post that Intel was expanding its Malaysian chipmaking facilities, which were first established in the 1970s. Intel Foundry President Naga Chandrasekaran has “made plans to begin the first phase” of the expansion, which will include advanced packaging, Ibrahim said.

“I welcome Intel’s decision to begin operations of the complex later this year,” a translated version of Ibrahim’s post said. Intel spokesman John Hebscher confirmed that it is working to build additional chip assembly and testing capacity in Penang, “amid growing global demand for Intel Foundry packaging solutions.”

Package store

According to Chandrasekaran, who took over Intel’s foundry operations in 2025 and spoke exclusively with WIRED while preparing this story, the term “advanced packaging” itself did not exist a decade ago.

Chips have always required some sort of integration between transistors and capacitors, which control and store energy. For a long time, the semiconductor industry has focused on miniaturization, or reducing the size of components on chips. As the world began demanding more computers in the 2000s, chips began to become denser with processing units, high-bandwidth memory, and all the necessary interconnecting parts. Eventually, chipmakers began taking a system-in-package or package-on-package approach, where multiple components are stacked on top of each other in order to squeeze more power and memory out of the same surface area. 2D stacking has given way to 3D stacking.

TSMC, the world’s leading semiconductor manufacturer, began offering packaging technologies such as CoWoS (chip-on-a-chip-on-a-substrate) and later SoIC (system-on-a-chip embedded) to customers. Essentially, the pitch was that TSMC would not only handle the front end of chipmaking — the chip part — but also the back end, where all the chip technology would be put together.

Intel had ceded chip manufacturing leadership to TSMC at this point, but continued to invest in packaging. In 2017, it introduced a process called EMIB, or Embedded Multi-die Interconnect Bridge, which was unique because it minimized the actual connections, or bridges, between components in the chip package. In 2019, it introduced Foveros, an advanced die stacking process. The company’s next packaging advance was an even bigger leap: EMIB-T.

Announced last May, EMIB-T promises to improve power efficiency and signal integrity between all components on chips. A former Intel employee with direct knowledge of the company’s packaging efforts told WIRED that Intel’s EMIB and EMIB-T are designed to be a more “surgical” way to package chips compared to TSMC’s approach. Like most chip developments, this is supposed to be more power efficient, save space and, ideally, save customers money in the long run. The company says the EMIB-T will be rolled out to factories this year.